We’re Hiring – Physical Design Engineer
Locations:
- Da Nang Office – 218 Bach Dang Street, Hai Chau District
Apply via email: hoai.doan@svctk.com
About the Role
As a Physical Design Engineer at SVC Technologies, you will take ownership of the full-chip physical implementation process — from netlist to tape-out. You will ensure that every design meets stringent standards of quality, performance, and manufacturability while collaborating closely with cross-functional and customer teams.
Key Responsibilities
1️ ⃣ Physical Design & Implementation (APR)
- Execute the complete RTL-to-GDSII flow, including floorplanning, placement, CTS, routing, and chip finishing.
- Perform congestion analysis, optimize PPA (performance, power, area), and ensure design closure.
- Manage partitioning and post-route optimization to meet design targets.
2️ ⃣ Timing Analysis & Closure
- Run multi-corner, multi-mode STA using industry-standard tools.
- Debug and resolve setup/hold violations and design rule violations (DRVs).
- Perform timing ECOs and collaborate with RTL and logic design teams for closure.
3️ ⃣ Physical Verification (PV)
- Conduct and debug DRC, LVS, LVL, PERC, and ERC checks.
- Ensure layout-to-netlist consistency and manufacturability compliance.
- Address density, antenna, and process-related issues effectively.
4️ ⃣ Power Integrity & Reliability
- Perform IR drop and EM analysis to ensure power integrity.
- Identify and mitigate voltage drop and PDN weaknesses.
- Propose and implement PDN improvements for optimized performance.
5️ ⃣ Automation & Tool Development
- Develop automation scripts using TCL, Perl, Shell, or Python to improve workflow efficiency.
- Contribute to methodology development, tool evaluation, and internal process automation.
- Provide technical support to internal teams and customers.
6️ ⃣ Quality, Reporting & Mentorship
- Follow best practices and sign-off checklists to ensure design integrity.
- Track project progress, assess risks, and report status to project leads.
- Mentor and support junior engineers when required.
Qualifications
- Bachelor’s or higher degree in Electrical Engineering, Telecommunications, VLSI, or Microelectronics.
- Minimum 3 years of hands-on experience in full-chip physical design (Netlist → GDSII).
- Proficient with tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, RedHawk/Voltus, and Calibre.
- Strong expertise in STA, ECO implementation, and sign-off closure.
- Solid understanding of IR/EM analysis and power integrity.
- Strong scripting skills (TCL, Perl, Shell, Python).
- Good English communication and teamwork skills.
Preferred Qualifications
- Experience with advanced technology nodes (28nm, 16nm, FinFET).
- Proven tape-out experience.
- Knowledge of low-power design techniques and multi-voltage domains (level shifters, isolation cells, etc.).
- Experience in team leadership or mentoring roles.
Why Join SVC Technologies?
- Competitive salary with performance-based bonuses.
- Comprehensive health insurance and annual check-ups.
- Generous paid leave and company welfare programs.
- Exposure to international projects and training opportunities.
- Potential rotation between Ho Chi Minh City and Da Nang offices.
Be part of the team shaping the next generation of semiconductor innovation.
Join SVC Technologies and bring your expertise to world-class chip design projects.
Apply now: hoai.doan@svctk.com
