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Arrive Technologies Viet Nam need to recruit 15 more Verification Design Engineers with the following job descriptions:
- Define verification plan, coverage plan based on Chip functionalities, standard, and application.
- Be responsible for Verification sign-off of various transport chips.
- For simulation field: Define/implement Block/System level test-bench based on the latest advanced verification methodologies (OVM, UVM …). Define/implement test cases following verification plans.
- For Emulation/Validation field: Verify chips at system level. Define/implement automation framework. Define/implement test cases following verification plans.
**Working conditions:
- To work at Etown Building, PCs with strong configuration, modern lab (telecom equipments and embedded systems in MAN/WAN networks, etc...)
- Competitive salary
- Dinner & parking allowance at Etown since probation time
- Other allowances: transportation, lunch, health insurance at international hospitals located in Viet Nam (such as Phap Viet, Colombia, Victoria Health Care, An Sinh,..)
Job Requirement:
-Bachelor of engineering, major in IC-Design/ Telecommunication/Electric-Electronics/IT/Software with GPA at least 7.0/10
- Telecommunication knowledge about Ethernet, MPLS, TCP/ IP…
- Familiar with Linux/Unix working environment.
- Good problem solving & communication skills.
- Good ability to read & understand telecommunication standards/ books or write reports in English.
Preferred:
- Familiar with design and verification tools: Cadence/Mentor Graphic, VCS...
- Expertise in chip design/verification languages: Verilog, System Verilog, C, C++…
- Familiar with Verification Methodologies: OVM, UVM…
- Familiar with script languages: Python, Perl, C-Shell, Bash-Shell, TCL…
**Interest candidates please send the resume and university score transcript via email jobs@atvn.com.vn with subject "Verification Design Engineer " or directly to the company address: Arrive Technologies Vietnam, 10th Fl, Etown Building (1), 364 Cong Hoa, Tan Binh Dist., HCM City, Vietnam before 25th of November, 2014.
nguồn: http://www.fetel.hcmuns.edu.vn/index...-25112014.html
- Define verification plan, coverage plan based on Chip functionalities, standard, and application.
- Be responsible for Verification sign-off of various transport chips.
- For simulation field: Define/implement Block/System level test-bench based on the latest advanced verification methodologies (OVM, UVM …). Define/implement test cases following verification plans.
- For Emulation/Validation field: Verify chips at system level. Define/implement automation framework. Define/implement test cases following verification plans.
**Working conditions:
- To work at Etown Building, PCs with strong configuration, modern lab (telecom equipments and embedded systems in MAN/WAN networks, etc...)
- Competitive salary
- Dinner & parking allowance at Etown since probation time
- Other allowances: transportation, lunch, health insurance at international hospitals located in Viet Nam (such as Phap Viet, Colombia, Victoria Health Care, An Sinh,..)
Job Requirement:
-Bachelor of engineering, major in IC-Design/ Telecommunication/Electric-Electronics/IT/Software with GPA at least 7.0/10
- Telecommunication knowledge about Ethernet, MPLS, TCP/ IP…
- Familiar with Linux/Unix working environment.
- Good problem solving & communication skills.
- Good ability to read & understand telecommunication standards/ books or write reports in English.
Preferred:
- Familiar with design and verification tools: Cadence/Mentor Graphic, VCS...
- Expertise in chip design/verification languages: Verilog, System Verilog, C, C++…
- Familiar with Verification Methodologies: OVM, UVM…
- Familiar with script languages: Python, Perl, C-Shell, Bash-Shell, TCL…
**Interest candidates please send the resume and university score transcript via email jobs@atvn.com.vn with subject "Verification Design Engineer " or directly to the company address: Arrive Technologies Vietnam, 10th Fl, Etown Building (1), 364 Cong Hoa, Tan Binh Dist., HCM City, Vietnam before 25th of November, 2014.
nguồn: http://www.fetel.hcmuns.edu.vn/index...-25112014.html
